Current Mirror Output Calculator

Several mechanisms cause the output current to deviate from the ideal mirror ratio. The most common are Vce mismatch (the output transistor operates at a different collector voltage than the reference transistor, so the Early effect shifts its current), base current loading (in BJTs, the base currents drawn from the reference node reduce the available reference current), and transistor mismatches (manufacturing variation in device geometry and doping). For precision applications, use a Wilson mirror or cascode mirror topology to suppress Vce sensitivity and base-current errors. For CMOS, use large-area transistors to minimize threshold mismatch and add cascode devices to improve output impedance.

Yes, current mirrors work for AC signals within their bandwidth. The bandwidth is limited by the transistor's transition frequency (fT) and by parasitic capacitances at the mirror nodes. The diode-connected reference transistor has significant input capacitance that, combined with any input source resistance, creates a low-pass pole. The Miller effect at the cascode node can also limit bandwidth in high-gain topologies. For wideband applications, choose high-fT transistors, minimize parasitic capacitances, and consider whether a simpler topology with lower output impedance might give better frequency response despite its lower DC accuracy.