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PCB Trace Width Calculator

Size minimum PCB trace width from target current and allowable temperature rise using the IPC-2221 standard external and internal tables. Free.

Frequently Asked Questions

Does trace length matter for current capacity?

Trace length does not affect the IPC-2221 current capacity formula, which is based entirely on the trace cross-section and the steady-state temperature rise. A 1 mm wide trace carries the same current whether it is 5 mm long or 500 mm long, from a thermal standpoint. However, longer traces have proportionally more resistance, which means more voltage drop and more total power dissipation spread over the trace length. If a 10 A trace is 300 mm long at 1 mm width and 1 oz copper, the resistance is approximately 500 mΩ and the voltage drop is 5 V, which is unacceptably high for a 12 V supply. In this case, the trace must be widened not for thermal reasons but to reduce voltage drop. Always check both temperature rise and voltage drop when sizing power traces.

What is the difference between IPC-2221 and Saturn PCB calculators?

IPC-2221 is the published industry standard document that defines the empirical equations for trace sizing. The Saturn PCB Toolkit is a widely used free software tool created by Saturn Electronics that implements the IPC-2221 equations along with additional features: trace resistance, inductance, voltage drop, via current capacity, differential pair impedance, and more. Saturn PCB does not define its own standard but applies IPC-2221 (and IPC-2152 for its newer routines) with additional derating options and cross-checks. When engineers refer to "Saturn PCB" as an authority, they mean they used the software as a convenient implementation of the IPC standard. Both this calculator and Saturn PCB implement the same underlying IPC-2221 equations and should give consistent results for standard inputs.

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Estimates for informational purposes only.

Important Disclaimer: Estimates for informational purposes only.

This calculator provides estimates for informational purposes only. Results are based on assumptions and may not reflect actual outcomes. Consult qualified professionals in relevant fields before making important decisions based on these results.

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How This Calculator Works

This tool sizes a PCB copper trace using the IPC-2221 external/internal conductor charts. The standard relates the cross-sectional area a trace needs to carry a given current within an acceptable temperature rise: Area (mils²) = (I ÷ (k × ΔT^0.44))^1/0.725, where k = 0.048 for external (surface) traces and 0.024 for internal (buried) traces, because outer layers shed heat better. The width then follows from the copper weight: width (mils) = Area ÷ (thickness_oz × 1.378), since 1 oz/ft² copper is about 1.378 mils thick. Enter current in amps, the allowable temperature rise (default 10°C), copper weight in ounces (default 1 oz), and the layer type.

Assumptions Behind the Number

IPC-2221 is empirical and conservative. It assumes a straight trace in still air at room ambient, with no nearby heat sources and no forced cooling. The temperature rise is the trace heating above ambient, so a 10°C rise on a board already running at 60°C means a 70°C conductor. The model says nothing about voltage drop along the trace - for long runs you may need to widen further just to hold supply tolerance. It also assumes a single isolated trace; copper pours and adjacent traces change the thermal picture.

When to Widen the Trace

Go wider than the minimum when the trace is long, when it sits next to other high-current traces, when the board has poor airflow or is conformally coated, or when reliability margin matters (automotive, industrial). For high-current power paths, prefer thicker copper (2 oz or more) over impractically wide traces, add copper pours, or stitch multiple layers with vias. Internal layers always need roughly double the width of an external trace for the same current because they cannot dissipate heat to open air.

IPC-2221 Reference & Related Tools

IPC-2221 (Generic Standard on Printed Board Design) superseded the older IPC-D-275 charts and is the most widely cited starting point for trace sizing; IPC-2152 is the newer, more detailed standard if you need higher accuracy. Treat this calculator's output as a conservative minimum to refine against your fabricator's capabilities and a real thermal review. Related tools: voltage drop calculator (for the conductor resistance side) and the LED series resistor calculator.

IPC-2221 Standard: The Two Governing Equations

IPC-2221 provides empirically derived equations for sizing PCB conductors. For an external (surface) trace, the required cross-sectional area in mils² is: A = (I / (0.048 x ΔT^0.44))^1/0.725. For an internal (buried) trace, the constant changes to 0.024, reflecting the reduced thermal dissipation through the surrounding laminate. These equations were derived by curve-fitting measured data from real PCB tests and represent conservative (safe) limits for the conditions they were tested under.

Once the required cross-sectional area is known, the trace width follows from the copper thickness. Standard copper weights in PCB fabrication are 0.5 oz, 1 oz, 2 oz, and 3 oz, corresponding to thicknesses of approximately 0.69, 1.378, 2.756, and 4.134 mils respectively (1 oz/ft² copper = 1.378 mils = 35 µm). The required width in mils equals the area divided by the thickness in mils.

Copper Weight and Trace Resistance

Copper weight affects not only current capacity but also trace resistance, which is critical for power delivery networks and precision analog circuits. The resistance per square of a trace is approximately 0.5 mΩ/square for 1 oz copper and 0.25 mΩ/square for 2 oz copper, derived from the copper resistivity of 1.72 x 10&sup8; Ωm and the copper thickness. A trace with a 10:1 length-to-width ratio (10 squares) in 1 oz copper has 5 mΩ of resistance, which at 1 A produces a 5 mV drop. For a 5 V rail, this is 0.1%, negligible; for a 1.0 V processor core rail, it is 0.5%, which can affect voltage regulator stability if multiplied across a long trace run.

Temperature Rise Limits

The IPC-2221 standard gives allowable current as a function of temperature rise above ambient. A 10°C rise is the standard conservative limit for most commercial applications and results in a trace temperature of approximately 35°C in a 25°C ambient. For high-reliability applications (automotive underhood, military, aerospace), a 20-30°C temperature rise limit is sometimes used, which corresponds to slightly wider traces. Increasing the allowable temperature rise to 20°C increases the allowable current by approximately 30% compared to a 10°C limit, or equivalently, reduces the required trace width for the same current.

Current Capacity Derating Factors

The raw IPC-2221 trace width is a starting point that should be derated for real-world conditions. Ambient temperature derating is required when the board operates above the 25°C reference temperature. As ambient increases, the trace can dissipate less heat to the environment, so for the same current the trace runs hotter. At 70°C ambient, the trace width should be increased by approximately 15-25% to maintain the same 10°C rise above local ambient. Conversely, a board with excellent airflow or forced cooling can sometimes use narrower traces than the standard suggests.

Adjacent trace coupling is another derating factor. When two high-current traces run parallel and close together, each trace heats the other. The rule of thumb is that traces closer than three times their width share significant thermal budget. For parallel power and ground traces in a DC-DC converter output, this mutual heating may require widening both traces beyond what a single-trace calculation would suggest.

Ground Planes and Thermal Relief

A solid copper ground or power plane on an adjacent layer dramatically increases the current-carrying capacity of traces because the plane provides a large thermal mass and spreading path for heat. A trace over a continuous ground plane may carry 50-100% more current than the IPC formula predicts for an isolated trace. However, solid copper pours reduce thermal relief at solder joints. Through-hole component pads connected directly to a copper pour lose heat rapidly during soldering, making it difficult to achieve good solder joints. Thermal relief spokes (a cross pattern of short traces connecting the pad to the pour) limit the heat flow during soldering while still providing the electrical connection. Most EDA tools add thermal relief automatically, but the designer should verify that high-current through-hole pads have thermal relief removed to minimize resistance.

Via Current Rating

Vias conduct current between PCB layers. Their current rating depends on the via diameter, plating thickness, and length (number of layers spanned). A rough rule of thumb is that a via carries approximately the same current as a trace with a width equal to the via's outer diameter, calculated using the IPC formula. Standard vias in a 2-layer board (0.3 mm drill, 0.1 mm plating) can carry approximately 500 mA to 1 A before temperature rise becomes significant. For high-current power paths, use multiple vias in parallel (stitch vias), larger via diameters, or filled/plated vias with greater copper cross-section. The minimum via annular ring (the copper ring surrounding the drill hole) is set by the PCB fabricator's capabilities and is typically 0.1-0.15 mm for standard processes.

Differential Pairs and High-Speed Routing

High-speed digital signals (USB, PCIe, SATA, Ethernet, LVDS) require controlled impedance traces whose width is determined by the need to match a specific characteristic impedance, not by current capacity. The characteristic impedance of a PCB microstrip trace is determined by the trace width, copper thickness, substrate height, and dielectric constant of the PCB material. Common impedance targets are 50 Ω for single-ended signals and 90-100 Ω differential for LVDS and USB. EDA tools with field solvers calculate the trace width required for each impedance target given the board stack-up.

Differential pairs must be routed with matched lengths within the tolerance required by the signaling standard. USB 2.0 requires length matching within 5 mm; PCIe Generation 3 requires within 1 mm; PCIe Generation 5 requires within 0.5 mm. Longer mismatches introduce inter-pair skew that converts common-mode noise into differential-mode noise and degrades bit error rate. Length matching is achieved by adding serpentine meanders (accordion bends) to the shorter trace of a pair.

EMC Return Path

At high frequencies, current returns to its source via the path of least inductance, not the path of least resistance. For a trace on the top layer of a PCB with a continuous ground plane on the bottom layer, the return current flows directly beneath the signal trace in the ground plane, forming a closely coupled microstrip transmission line with controlled impedance and minimal loop area. Any interruption of the ground plane beneath the trace (a cutout, a slot, or a plane split) forces the return current to detour around the interruption, greatly increasing the loop area and the radiated EMI. This is why cutting slots in ground planes beneath high-speed signals is one of the most common PCB EMC design errors, and why ground planes should be kept continuous beneath signal traces whenever possible.

Necking Down

Many IC pads and connector footprints have pad pitches that require the connecting trace to narrow (neck down) from the wider routing trace to the smaller pad. This is unavoidable but should be minimized in length. The necked-down section is the current bottleneck and is the hottest part of the trace. For power traces, the necked section may need to be verified against the IPC formula at the minimum width, not at the wider routing width. For high-speed signals, necking down changes the trace impedance and can cause reflections if the necked section is longer than about 1/10 of the signal's rise-time wavelength.

DFM Considerations

PCB fabricators have minimum feature sizes that constrain trace widths and spacings. Standard two-layer PCBs from budget fabricators (JLCPCB, PCBWay) support minimum trace width and spacing of 0.1 mm (4 mil). Standard four-layer boards are similar. Advanced processes support 0.075 mm (3 mil) minimum features, and HDI (high-density interconnect) processes for mobile devices achieve 0.05 mm (2 mil) or less. Designing traces narrower than the fabricator's minimum capability results in open circuits or yield loss. Always verify trace widths against the fabricator's published design rules before finalizing the layout.